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SX1210
ADVANCED COMMUNICATIONS & SENSING
6.3. Interrupt Configuration Parameters - IRQParam
The detailed description of the IRQParam register is given in Table 23.
Table 23: IRQParam Register Description
Name
Bits
Address
(d)
RW
Description
IRQ_0 source in Rx and Standby modes:
If Data_mode(1:0) = 00 (Continuous mode):
00
01
10
11
Sync (d)
RSSI
Sync
Sync
If Data_mode(1:0) = 01 (Buffered mode):
00
- (d)
Rx_stby_irq_0
7-6
13
r/w
01
Write_byte
10
11
/Fifoempty*
Sync
If Data_mode(1:0) = 1x (Packet mode):
00
01
10
11
Payload_ready (d)
Write_byte
/Fifoempty*
Sync or Adrs_match (the latter if address filtering is enabled)
*also available in Standby mode (Cf sections 5.4.3 and 5.5.6)
IRQ_1 source in Rx and Standby modes:
If Data_mode(1:0) = 00 (Continuous mode):
xx
DCLK
If Data_mode(1:0) = 01 (Buffered mode):
00
01
- (d)
Fifofull*
Rx_stby_irq_1
5-4
13
r/w
10
11
RSSI
Fifo_threshold*
If Data_mode(1:0) = 1x (Packet mode):
00
01
10
11
CRC_ok (d)
Fifofull*
RSSI
Fifo_threshold*
*also available in Standby mode (Cf sections 5.4.3 and 5.5.6)
Fifofull
/Fifoempty
Fifo_overrun_clr
2
1
0
13
13
13
r
r
r/w/
c
Fifofull IRQ source
Goes high when FIFO is full.
/Fifoempty IRQ source
Goes low when FIFO is empty
Goes high when an overrun error occurred. Writing a 1 clears flag and FIFO
FIFO filling method (Buffered mode only):
Fifo_fill_method
7
14
r/w
0
Automatically starts when a sync word is detected (d)
1
Manually controlled by Fifo_fill
FIFO filling status/control (Buffered mode only):
Fifo_fill
6
14
r/w/
c
If Fifo_fill_method = ‘0’: (d)
Goes high when FIFO is being filled (sync word has been detected)
Writing ‘1’ clears the bit and waits for a new sync word (if Fifo_overrun_clr=0)
Rev 2– Sept 8 , 2008
th
Page 51 of 73
www.semtech.com
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